Date Morning Afternoon Location

December 10, 2018

PYNQ: Python productivity for Zynq

Date: Dec 10, Full day
Topic: Zynq FPGA, Hands-on
Organizer(s): Xilinx
Type: Tutorial WS
Details: PYNQ is an open-source framework that enables programmers who want to use embedded systems to exploit the capabilities of Xilinx Zynq SoCs. It allows users to exploit custom hardware in the programmable logic without having to use ASIC-style CAD tools. Instead the SoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed.
The framework combines four main elements: (1) the use of a high-level productivity language, Python in this case; (2) Python-callable hardware libraries based on FPGA overlays; (3) a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynq's embedded processors; and (4) Jupyter Notebook's client-side, web apps. The result is a web-centric programming environment that enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries.
This tutorial will give a hands-on introduction to PYNQ framework using recently introduced PYNQ-Z2 board. It will feature the latest PYNQ release which includes an updated API, an optimized video pipeline, a simplified way of integrating new hardware and drivers into PYNQ, and developing, compiling, and deploying C-language code straight from the Jupyter notebook without opening Xilinx SDK tool.
Note: Attendees will use their laptops to connect to the board. We would like to ask all attendees to prepare PNYQ-Z2 board and basic accessories (Ethernet cable, MicroUSB cable, SDCard, and Power Supply) in advance and bring it on the day of the workshop. Please contact FPT18-PYNQ-WS@AVNET.COM for more details.

December 11, 2018

Workshop on Xilinx AWS

Date: Dec 11, Full day
Topic: AWS, Hands-on
Organizer(s): Xilinx
Type: Tutorial WS
Details: FPGA-based Accelerated Cloud Computing with SDAccel
The increasing computational requirements of next-generation Cloud and High-Performance Computing (HPC) applications are pushing the adoption of accelerated computing based on heterogeneous architectures into mainstream, as traditional CPU technology is unable to keep pace.
Xilinx FPGAs are now available, in two different sizes that include up to eight Virtex® UltraScale+ VU9P, on the Amazon Elastic Compute Cloud (EC2) F1 instances, which are designed to accelerate data center workloads, including machine learning inference, data analytics, video processing, and genomics. Furthermore, Amazon Web Services offers the SDAccel™ Development Environment for cloud acceleration, enabling the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto the heterogeneous CPU-FPGA system.
SDAccel completely automates the step of the hardware design flow, offering an easy to use environment for FPGA application design. It offers the possibility to specify a compute kernel using C and C++ for higher-level algorithmic implementation, or using hardware description languages for RTL designs, while using OpenCL APIs to control run-time behavior.
Attendees will use their laptops to connect to the EC2 F1 instances.

Workshop on Integrating HPC and FPGAs

Date: Dec 11, Half day (morning)
Topic: high-performance computing, emerging workloads
Organizer(s): Argonne National Laboratory, Center for Computational Sciences,University of Tsukuba, RIKEN R-CCS, JLESC, IWFH
Type: Invited talks/panel discussions
Details: Traditionally, high-performance computing (HPC) platforms have been designed for relatively regular and floating-point intensive-workloads (e.g., LINPACK). Because of emerging artificial intelligence, big data, and data analytics requirements, HPC platforms need to be changed to accommodate such workloads as well as traditional ones. Since FPGAs have already demonstrated their acceleration potential for these new HPC requirements, integrating FPGAs into HPC is a natural step. In this workshop, HPC experts who have been evaluating FPGAs for HPC will discuss challenges and opportunities of such integration. Our goal is to initiate new strong collaborations between FPGA experts and HPC experts. This workshop is co-held with the International Workshop on FPGA for HPC (IWFH), the Joint Laboratory on Extreme Scale Computing (JLESC), and the Field-Programmable Technology Workshop (FPT'18). Audience participation is highly encouraged.

Workshop on Reconfigurable High-Performance Computing

Date: Dec 11, Half day (afternoon)
Topic: high-performance computing, programming models, FPGA runtime systems, HPC cluster technologies, network/storage acceleration
Organizer(s): Argonne National Laboratory, Center for Computational Sciences,University of Tsukuba, National Institute of Advanced Industrial Science and Technology
Type: Invited talks/panel discussions
Details: Reconfigurable computers are expected to play an important role in the post-Moore era, offering a true co-design vehicle that could significantly improve both the performance and the energy efficiency of computation. While FPGAs-accelerated systems are becoming practical in the cloud and data centers, FPGAs or reconfigurable computers are still not common in large HPC systems. In this workshop, we will discuss future workloads, programming models, network/storage acceleration and clustering technologies that can enable reconfigurable high-performance computing. Audience participation is highly encouraged.

December 14, 2018

Introduction to BLE system design using PSoC 6MCUs

Date: Dec 14, Half day (afternoon)
Topic: Development with a hands-on lab using PSoC 6 BLE for IoT node
Organizer(s): Patrick Kane, Cypress Semiconductor Corp.
Type: Hands on tutorial WS
Details: The proposed workshop will introduce attendees to available development kits suitable for education and will include a hands-on lab using PSoC 6 BLE – based development kit to create and program a BLE enabled development kit thus creating a simple IoT node. The ultra-low-power PSoC 6 MCU architecture offers the processing performance needed by IoT devices. The PSoC 6 MCU contains a dual-core architecture, with both cores on a single chip. It has an Arm® Cortex®-M4 for high-performance tasks, and an Arm® Cortex®-M0+ for low-power tasks, and with security built-in, your IoT system is protected.

Embedded Machine Learning: Technology and Opportunities

Date: Dec 14, Half day (afternoon)
Topic: Embedded machine learning discussion with specialists
Organizer(s): David Boland and Philip Leong
Type: Tutorial WS
Details: This workshop will provide a forum to discuss technical challenges and product opportunities for applying deep learning within embedded systems that take advantage of the energy and latency benefits offered by field programmable gate arrays (FPGAs).

Accelerate real-time high definition video processing designs with Digilent Zybo Z7, a Zynq-7000 AP SoC Platform and Xilinx Vivado HLS

Date: Dec 14
Topic: Hands-on tutorial using a Zynq FPGA
Organizer(s): Digilent
Type: Hands-on tutorial WS
Details: It is a hands-on tutorial using a Zynq FPGA with HLS to design a streaming hardware.
Details (PDF) »

Call for Workshop Proposals

We closed the call for workshop proposals.

Following the success from previous editions, FPT 2018 will host several workshops on December 11th & 15th, 2018. We are soliciting proposals for new and recurring workshops to be organized with FPT 2018, as they provide excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere, and to foster collaboration for new and innovative projects. We invite you to submit workshop proposals on any topic related to the broad set of Architectures and Technology, Applications and Benchmarks, Design Methods and Tools, Self-aware and Adaptive Systems, and Trends and Education before the deadline of March 16, 2018 (extended)

We strongly encourage workshops that focus on innovative and original ideas related to the core topics of FPT. Organizers can choose between invited presentations (to be listed at the time of submission), open call for papers, or a combination of both. Any other forms of interaction with the audience - panels, demo's, posters - are of course welcome, as we see workshops providing as many and dynamic forms of engaging the audience as possible.

For workshops that do include an open call for papers, we point out that the organizers are in charge of setting up the submission, review, and camera-ready management processes. The organizers must also indicate what their expectation for the workshop is (papers submitted, papers accepted).

Workshop organizers are free to arrange the publication of their workshop papers independently. FPT 2018 does not provide workshop proceedings, but may consider including the workshop papers on the conference website, as long as the workshop organizers can provide their final papers in time.

Call for Workshop Proposals in PDF »

Workshop proposal submission requirements

To submit a workshop proposal, please prepare a PDF file (2 pages max, excluding biographies and references), including the following information:

Please send your proposals by email ( to the FPT 2018 Workshop Chair.

Proposal submission due

March 16, 2018 (extended) (closed)

FPT2018 Workshop Chair

Hiroki Nakahara, Tokyo Institute of Technology, Japan