Title: FPGA Accelerated HPC and Data Analytics
Abstract: There are increasing opportunities in the data center for FPGA algorithm, networking, and data access acceleration. Microsoft has announced that they accelerate Bing search, machine learning, and networking with FPGAs – and they recently announced integration of FPGA based Project Brainwave with Azure Machine Learning for real-time AI. FPGAs also deliver some futureproofing for AI, with current support for reduced precision floating point and bfloat16 for better performance with minor loss of scoring accuracy. Intel and partners are also integrating FPGAs to data analytics frameworks and existing databases to enable enterprise customers to run unmodified applications without requiring any FPGA expertise for use with unstructured, NoSQL, and traditional relational databases. One such partner, Swarm64, is using a single FPGA for multiple acceleration roles to deliver 2X+ performance on the industry standard TPC-H benchmark.
Biography: Mike Strickland has more than twenty years of computer, networking and storage experience with companies such as Hewlett Packard, Silverback Systems, and Altera, which is now a part of Intel. He currently is leading the FPGA High Performance Computing vision across the Programmable Solutions Group at Intel. Previously Strickland has led the development and launch of numerous products including networking, storage management, TCP/IP Offload and iSCSI. He holds a B.S. degree in electrical engineering from Brown University and a M.S. degree in management from the Sloan School of Management at M.I.T.
Title: Accelerator-in-Switch: a novel cooperation framework for FPGAs and GPUs
Abstract: A large-scale FPGAs have been used as high-performance switches which connect powerful computational accelerators including GPUs. In most cases, the FPGA has a room of implementing additional accelerators which can treat on-the-fly data in the switch directly. Here, we introduce two implementation examples: one is for a low latency switching hub PEACH3 for high-performance scientific computing, and the other is FiC-SW for AI computing in a cloud. The key technique is how to use the partial reconfiguration and HLS description for the accelerator-in-switch.
Biography: Hideharu Amano received Pd.D from Keio University, Japan in 1986. He is now a professor, Dept of Information and Computer Science, Keio University. His research interests include parallel architectures and reconfigurable computing.
Title: Novel Neural Network Applications on New Python Enabled Platforms
Abstract: Reconfigurable technology is very well suited for novel implementations of neural networks. In this presentation we will show the range of implementations for neural networks on reconfigurable technology. This includes a direct dataflow implementation of networks, and implementations of an ‘soft’ processor using an array of DSP blocks. We will show the trade-offs in implementation cost and power over a range of implementations with varying bit-precisions. These implementations are leveraging novel python based abstractions, that support a Jupyter Notebook interface. We will illustrate this with complete implementations on embedded platforms including the Pynq platform and on cloud based platforms including the AWS F1 platform. Finally we will project the new possibilities of the new 7nm based Xilinx platforms that contain specialized hardware that is very efficient for these neural network applications.
Biography: Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW –SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University, where he worked on early High Level Synthesis tools. He was a visiting industrial fellow at UC Berkeley where he worked on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. For more than a decade he is heading a team of researchers at Xilinx, including a significant part of the Xilinx European Laboratories. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, machine learning applications and architectures, wireless applications and new datacenter applications. He has been instrumental in the High-Level Synthesis technology and one of the technical leads in the novel ACAP technology. He is now a Fellow at Xilinx.
Title: Digital Transformation of Automobile and Mobility Service
Abstract: Automobile traffic system has not changed its physical, industrial and social structure more than 100 years from its start. It has been deployed in large scale, and it has realized important role of mobility. It consists of driver, automobile, and road physically. The system elements have been physically contacted each other and have been managed only by human. Electric and electronic technology have improved performance of automobile mechanic system for more than 30 years. The digital transformation Era is beginning. The system elements will have a digital data connection. The system value, size, range, and role will change dramatically. CASE；Connected Car, Autonomous Driving, Sharing Car and Mobility as a Service, Electrification make large-scale innovation of not only automobile but automobile traffic system, automobile industry and society. We will outline these new system and service concept. Then we will describe these digital transformation process will continue for a long time because the system and service will change year by year, which people are involved in. We will discuss the need for data cycle for improvement of this system and service. We will mention technologies needed for the future Mobility IoT and Automobile digital transformation such as communication technologies, drive by wire technology, drive by information technologies, traffic management technology by ICT, IoT technology, cloud technology that has scalability, flexibility, security, traceability, safety, reliability.
Biography: Hiroshi Miyata is a fellow at FUJITSU LABORATORIES LTD. He researches Mobility IoT related technologies and systems from 2017. He received M.S from the University of Tokyo in 1981. He was an engineer at Toyota Motor Corp.(TMC) from 1981 to 2004. He developed the first automobile shock absorber electronic control system and developed suspension systems, Cruise Control system, throttle system by wire, Electronic Control Units, sensors, and actuators. He planned car electronics technologies strategies in 1994. He promoted system integration called “Intelligent Transportation System” at Fujitsu Ten Ltd. from 1995 to 1996. He developed car multimedia systems, such as car navigation, emergency-call, connected car system from 1997 to 2004 at TMC. He was a president of Toyota InfoTechnology Center that is a research center of Information Communication technologies for automobile from 2005 to 2007. He was a general manager of electronics engineering Div. I at TMC from 2008 to 2009. He was a Managing Officer at TMC from 2009 to 2011. He was an executive Vice President of Toyota Technical Development Ltd from 2011 to 2016.